Ausdia, a leader in design constraints verification and management, unveiled Timevision OneSource at DAC 2025 in San Francisco. This innovative solution addresses a critical gap in SoC design by automating the translation of Synopsys Design Constraints (SDC) to align with post-optimization netlists, preserving the integrity of hand-crafted constraints while supporting advanced design transformations.
Timevision OneSource launched at DAC 2025 for SoC design optimization.
Automates SDC constraint translation for post-optimization netlists.
Eliminates manual constraint adaptation, saving time and reducing errors.
Maintains readable, source-form constraints for design signoff.
Integrates with Timevision platform, supporting over 1 billion cells.
Enhances power, performance, and area (PPA) without sacrificing constraint quality.
Timevision OneSource tackles the challenge of maintaining usable SDC constraints after modern optimization engines restructure chip designs. These engines dissolve hierarchies, merge flops, and perform transformations like flop banking and cloning to improve power, performance, and area (PPA). However, such changes often render original constraints incompatible. OneSource automates the translation process, ensuring constraints remain functional and accurate throughout the design flow.
"The shift-left methodology has led design teams to create sophisticated, programmable constraint files that map correctly and consistently on their original RTL designs," said Sam Appleton, Ausdia CEO. "However, when optimization tools restructure hierarchies, merge flops, and clone elements to achieve better PPA, those golden constraints no longer map to the transformed design. OneSource solves this critical gap by automatically translating source constraints to work seamlessly with post-optimization netlists." This automation eliminates manual intervention, reducing errors and accelerating design timelines.
Timevision OneSource offers several advantages for SoC design teams. It preserves source-form constraints for clear, readable signoff checks while generating chip-level constraints compatible with optimized netlists. The solution includes robust verification to ensure translation accuracy and seamlessly integrates with pre- and post-optimization environments. "OneSource represents a breakthrough in constraint management technology," Appleton said. "Design teams no longer need to choose between achieving optimal PPA through advanced optimization and maintaining clean, understandable constraints. Our solution delivers both automatically."
OneSource enhances the Timevision platform, known for handling over 1 billion cells and thousands of clocks across the design flow. From pre-synthesis to signoff timing, it supports comprehensive constraint development, verification, and management. This integration ensures OneSource aligns with existing workflows, making it a vital tool for complex SoC designs in AI, HPC, and automotive applications.
Ausdia’s Timevision OneSource, showcased at DAC 2025, sets a new standard for constraint management in SoC design. By automating SDC translation and ensuring compatibility with optimized designs, it empowers engineers to achieve superior PPA without compromising constraint integrity, streamlining the path to design closure.
Founded in 2006 and headquartered in Sunnyvale, California, Ausdia delivers standout timing constraint development, verification, and management solutions that complement all implementation and timing signoff flows. Ausdia’s customers include leading semiconductor companies worldwide, and the company’s solutions are used extensively in the development of SoCs and ICs for AI, HPC, and automotive.
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