Synopsys has announced expanded collaboration with Intel Foundry to certify AI-powered electronic design automation (EDA) flows for Intel 14A process technology. Revealed at the 2026 DAC Chips to Systems Conference, the collaboration advances semiconductor design enablement from traditional design technology co-optimization (DTCO) toward system-aware co-design for next-generation AI and high-performance computing (HPC) applications.
The expanded partnership builds on Synopsys' certified, production-ready EDA flows and intellectual property (IP) portfolio supporting Intel 18A and Intel 18A-P technologies. Together, the companies aim to help chip designers address increasing complexity across advanced process nodes, multi-die architectures, packaging, and system-level performance optimization.
As semiconductor designs move beyond traditional monolithic scaling, chip manufacturers and designers require more advanced approaches to manage power, performance, area, and system-level reliability. Synopsys' AI-powered EDA flows are designed to help engineers optimize complex designs by connecting process technology, advanced packaging, multiphysics analysis, and IP integration.
According to Synopsys, angstrom-scale semiconductor development requires predictable system outcomes rather than simply improving individual process-node metrics. The company's collaboration with Intel Foundry focuses on accelerating design convergence, reducing late-stage design changes, and improving first-pass silicon success.
"Angstrom-scale design is no longer only about extracting more power, performance, and area from a process node. It is about turning process innovation into predictable system-level outcomes," said Michael Buehler-Garcia, Senior Vice President at Synopsys. "Together with Intel Foundry, Synopsys is helping customers accelerate convergence, reduce late-stage rework, and achieve first-pass silicon success. We applaud the Intel Foundry team for their progress on Intel 14A to expand the capabilities of advanced semiconductor manufacturing."
"In this increasingly AI-driven world, Intel Foundry is committed to supporting our customers by accelerating innovation and providing predictable execution from silicon to packaging on our most advanced technologies," said Shawn Han, SVP and GM, Foundry Services, Intel Corporation. "Our wide-ranging collaboration with Synopsys, including AI-driven, certified flows and IP, gives our customers greater ease of use and confidence to achieve their design goals."
At advanced semiconductor geometries, challenges involving electrical performance, thermal behavior, and mechanical reliability can no longer be evaluated separately. Increasing transistor density, backside power delivery, and three-dimensional integration require a unified design approach.
Synopsys is addressing these challenges through the integration of certified AI-powered implementation and signoff flows with multiphysics analysis capabilities. These solutions evaluate power integrity, thermal performance, and electromagnetic effects on Intel 14A technology, helping designers identify potential system-level issues earlier in the development cycle.
By combining EDA automation with advanced analysis capabilities, engineers can improve design accuracy while reducing risks associated with increasingly complex semiconductor architectures.
Multi-die and chiplet-based architectures have become essential for AI and HPC applications as companies look for scalable alternatives to traditional chip designs. Synopsys and Intel Foundry are extending their collaboration to support system-level integration, optimization, and verification for advanced multi-die solutions.
The Synopsys reference design flow based on 3DIC Compiler supports Intel Embedded Multi-die Interconnect Bridge (EMIB) and Embedded Multi-die Interconnect Bridge-T (EMIB-T) packaging technologies. The solution enables early bump and TSV planning, automated UCIe and HBM routing, and unified multiphysics analysis across dies and packaging components.
Design teams can analyze power delivery networks, thermal gradients, and signal integrity across chiplets, interconnects, and packages during the design stage instead of discovering issues after tapeout.
Synopsys and Intel Foundry are also expanding ecosystem readiness through a broader portfolio of high-performance interface and foundation IP designed for AI and HPC workloads.
The expanded IP portfolio includes support for Intel 14A technologies while continuing availability across Intel 18A and Intel 18A-P processes. These solutions aim to reduce integration challenges and accelerate time-to-tapeout for advanced systems-on-chip (SoCs) and multi-die designs.
Key IP advancements include:
Through its collaboration with Intel Foundry, Synopsys is helping semiconductor companies build more predictable, scalable, and efficient design processes for AI-driven computing systems.
Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
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