Synopsys, Inc. has deepened its collaboration with TSMC to deliver advanced electronic design automation (EDA) and intellectual property (IP) solutions, enabling innovative AI chip and multi-die designs on TSMC’s cutting-edge processes.
Synopsys and TSMC enhance AI chip and multi-die design solutions.
Certified EDA flows on TSMC’s N2P and A16 processes boost performance.
3DIC Compiler supports TSMC’s SoIC and CoWoS for 3D integration.
AI-optimized photonic flow enhances TSMC-COUPE for multi-die designs.
Comprehensive IP portfolio supports HBM4, PCIe 7.0, and automotive nodes.
Collaboration accelerates time-to-market for energy-efficient AI chips.
Synopsys, Inc. (Nasdaq: SNPS) has strengthened its partnership with TSMC to provide multi-die solutions, integrating advanced EDA tools and IP products tailored for TSMC’s leading-edge processes like N2P and A16. This collaboration has led to multiple customer tape-outs, leveraging Synopsys’ 3DIC Compiler platform for 3D packaging and design enablement, driving innovation in AI chip and multi-die architectures.
Synopsys’ digital and analog EDA flows, powered by Synopsys.ai, are certified for TSMC’s N2P and A16 processes using TSMC NanoFlex architecture. These flows optimize performance, power, and scalability for advanced semiconductor designs. Michael Buehler-Garcia, Senior Vice President at Synopsys, stated, “With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC’s advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market.” The partnership also supports TSMC’s A16 Super Power Rail process, improving power distribution and thermal robustness.
The Synopsys 3DIC Compiler supports TSMC’s SoIC and CoWoS technologies, enabling automated UCIe and HBM routing, TSV planning, and multi-die signoff verification. This has resulted in successful customer tape-outs for 3D stacked designs. Additionally, Synopsys and TSMC’s collaboration on silicon photonics has introduced an AI-optimized photonic IC flow for TSMC-COUPE technology, addressing multi-wavelength and thermal challenges in AI-driven multi-die designs.
Synopsys offers a robust IP portfolio for TSMC’s N2P/N2X, N5A, and N3A processes, supporting high-performance standards like HBM4, 1.6T Ethernet, UCIe, and PCIe 7.0. Aveek Sarkar, Director at TSMC, noted, “With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows and high-quality IP to meet or exceed their design targets.” This portfolio ensures safety, security, and reliability for automotive, IoT, and HPC applications.
The collaboration between Synopsys and TSMC is paving the way for next-generation AI and multi-die designs, enabling businesses to meet rising computational demands with energy-efficient, high-performance solutions. By combining certified tools and IP, the partnership accelerates innovation across industries.
Synopsys, Inc. (Nasdaq: SNPS) is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Learn more at www.synopsys.com.
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