Synopsys, Inc. and Samsung Foundry have deepened their collaboration to drive next-generation AI, high-performance computing (HPC), and edge AI designs. Announced on June 16, 2025, this partnership leverages Synopsys’ AI-driven EDA tools and IP portfolio alongside Samsung’s advanced SF2P and I-CubeS technologies, enabling faster, more efficient chip development.
Synopsys and Samsung achieve HBM3 tape-out on SF2P with 10X faster turnaround.
Certified AI-driven EDA flows for SF2P accelerate high-performance designs.
Synopsys’ 3DIC Compiler enhances multi-die designs with 6% better performance.
New IP portfolio, including 224G, UCIe, and LPDDR6, optimized for SF2P and SF4X.
Collaboration improves power, performance, and area (PPA) for AI applications.
Supports edge AI, HPC, IoT, automotive, and consumer electronics markets.
The collaboration has yielded a successful HBM3 customer tape-out on Samsung’s SF2P process using Synopsys’ 3DIC Compiler, reducing turnaround time by 10X. “The adoption of Edge AI applications is driving the need for advancements in semiconductor technologies to enable complex computational tasks, improve efficiency, and expand AI capabilities across various industries and applications,” said John Koeter, senior vice president for the Synopsys IP Group. The partnership supports a range of applications, from data center AI inference engines to edge devices like cameras and drones.
Synopsys’ AI-driven digital and analog flows, certified for Samsung’s SF2P process, leverage the Synopsys.ai full-stack EDA suite to enhance PPA. “Synopsys and Samsung have deepened their collaboration to optimize PPA for designs using Samsung’s advanced technologies,” said Hyung-Ock Kim, vice president and head of the Foundry Design Technology Team at Samsung Electronics. A new schematic migration flow, powered by Synopsys ASO.ai, enables efficient migration of SF4 analog IPs to SF2P, streamlining development for high-performance SoCs.
The Synopsys 3DIC Compiler, paired with Samsung’s I-CubeS 2.5D packaging and X-Cube technology, supports complex multi-die designs. It achieved a 6% improvement in worst-case eye opening for HBM routing, completed in just four hours, enhancing performance and reliability. The compiler’s rapid 3D floorplanning, bump, and Through-silicon via (TSV) planning, along with early thermal analysis, ensures efficient multi-die integration for advanced AI and HPC applications.
Synopsys offers a robust IP portfolio optimized for Samsung’s SF2P, SF4X, and other advanced nodes, including 224G, UCIe, PCIe 7.0, MIPI, LPDDR6X, and USB4. This portfolio, covering embedded memories, logic libraries, and security IP, supports applications in HPC, mobile, IoT, and automotive markets. By reducing integration risks, Synopsys accelerates time-to-market for chipmakers, ensuring competitive, high-performance designs.
This collaboration between Synopsys and Samsung Foundry empowers mutual customers to deliver cutting-edge AI and multi-die designs with superior efficiency, performance, and scalability, driving innovation across industries.
Catalyzing the era of pervasive intelligence, Synopsys, Inc. delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
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