Arteris, Inc., a leading provider of system IP, has expanded its multi-die solution to accelerate chiplet-based semiconductor designs for AI and high-performance computing. This update delivers standards-based, automated tools to streamline integration, reduce design time, and enhance performance for next-generation silicon.
Arteris’ multi-die solution boosts AI and HPC chiplet design efficiency.
Supports UCIe, Arm AMBA, and PCIe for seamless interoperability.
FlexNoC and Ncore NoC IP enable robust die-to-die communication.
Magillem automation reduces SoC assembly risks and speeds integration.
Collaborations with Arm, Cadence, Renesas, and Synopsys drive innovation.
Solution optimizes power, performance, and area for AI workloads.
As Moore’s Law slows, AI workloads demand innovative architectures beyond traditional monolithic designs. Arteris’ expanded multi-die solution enables chiplet-based systems, offering scalable, high-performance solutions for AI and automotive applications. “In the chiplet era, the need for computational power increasingly exceeds what is available by traditional monolithic die designs,” said K. Charles Janac, president and CEO of Arteris.
The solution supports Universal Chiplet Interconnect Express (UCIe), Arm AMBA protocols, and PCIe, ensuring compatibility across IP cores, chiplets, and SoCs. Integration with EDA and foundry partners like Cadence, Synopsys, and global fabs provides a ready-to-deploy ecosystem, accelerating time-to-market for semiconductor innovators.
Arteris’ silicon-proven FlexNoC IP facilitates non-coherent die-to-die communication, integrating with third-party controllers and PHYs. The new Ncore NoC IP supports cache-coherent reads and writes across chiplets, simplifying multi-die systems to function as a single silicon unit for software developers, enhancing performance and scalability.
Magillem Connectivity and Registers automation optimizes SoC creation by reducing manual integration risks. These tools streamline workflows from system map definition to validation, ensuring a single source of truth for hardware and software integration, minimizing errors, and accelerating development cycles.
Arteris collaborates with industry leaders to drive chiplet innovation. Arm supports interoperable chiplet ecosystems via AMBA CHI C2C specifications. Cadence and Synopsys enhance EDA tool flows for optimized multi-die designs. Renesas leverages Arteris technology in its R-Car Gen 5 platform for ADAS, while RISC-V partners like SiFive and Tenstorrent support domain-specific chiplets. “By collaborating with Arteris, we’re accelerating the journey to chiplet-based systems,” said David Glasco, vice president of R&D at Cadence.
The multi-die solution compresses development cycles and enables modular architectures tailored for AI and automotive platforms. “Arteris technology plays a key role in realizing this vision by providing the underlying connectivity in our 5th generation R-Car automotive silicon,” said Aish Dubey, vice president at Renesas. This approach delivers differentiated performance while aligning with industry standards.
Arteris’ expanded multi-die solution empowers semiconductor firms to innovate rapidly, addressing the computational demands of AI and high-performance computing. By optimizing power, performance, and interoperability, it paves the way for scalable, efficient chiplet-based designs.
Arteris is a global leader in system IP used in semiconductors to accelerate the creation of high-performance, power-efficient silicon. Arteris network-on-chip (NoC) interconnect IP and system-on-chip (SoC) integration automation software are used by the world's top semiconductor and technology companies to improve overall performance, engineering productivity, reduce risk, lower costs, and bring complex designs to market faster.
TechIntelPro empowers B2B technology decision-makers with the latest industry trends, deep insights, leadership perspectives and actionable intelligence to drive both organizational and professional milestones—and thrive on the tech pulse.